They’ll develop U.S.-made ASIC chips and work with American universities to develop security technologies to enhance data and intellectual property protection.
Intel and the U.S. Defense Advanced Research Projects Agency announced a partnership today that is created to advance a semiconductor supply chain security as well as domestic manufacturing in the U.S. Intel and DARPA will develop U.S.-made Application Specific Integrated Circuits, also known as ASIC chips, and work with American universities to develop security technologies to enhance data and intellectual property protection.
“It’s all being made within the U.S. from beginning to end,” said José Roberto Alvarez, senior director, CTO office, Intel programmable solutions group, in a press release. “This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel’s advanced 10nm semiconductor process.”
Called the Structured Array Hardware for Automatically Realized Applications, or SAHARA for short, the partnership will enable the design of custom chips with security countermeasure technologies. A reliable, secure, domestic source of leading-edge semiconductors remains critical to the US, the press release announced.
Intel eASIC devices are “structured ASICs, an intermediary technology between field-programmable gate arrays (FPGAs) and standard-cell ASICs,” the press release explained. “These devices provide lower unit-cost and run on lower power compared with FPGAs and provide a faster time to market and lower non-recurring engineering cost compared with standard-cell ASICs.”
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“Structured ASICs have advantages over FPGAs that are widely used in many Department of Defense applications,” said Serge Leef, a program manager in DARPA’s microsystems technology office, in the press release. “In partnering with Intel on the SAHARA program, DARPA aims to transform currently fielded as well as future capabilities into structured ASIC implementations with significantly higher performance and lower power consumption. SAHARA aims to dramatically shorten the ASIC design process through automation while adding unique security features to support manufacturing of the resulting silicon in zero-trust environments. Additionally, Intel will establish domestic manufacturing capabilities for the structured ASICs on their 10nm process.”
Intel will develop security countermeasure technologies that enhance protection of data and intellectual property from reverse engineering and counterfeiting in a collaboration with the University of Florida, Texas A&M and University of Maryland. Using rigorous verification, validation and new attack strategies to test the security of these chips will be done at the schools. Security countermeasure technologies will be integrated into Intel’s structured ASIC design flow.
Through its structured ASIC technology, Intel will develop platforms that accelerate development time and reduce engineering cost, compared to traditional ASICs. Using its 10nm process technology, Intel will manufacture these chips with the advanced interface bus die-to-die interconnect and embedded multi-die interconnect bridge packaging technology to integrate multiple heterogeneous die in a single package.